Design and VHDL implementation of 32 bit ALU
The objective of the project is to implement a 32-bit Arithmetic Logic Unit (ALU) from a central processing unit using VHDL. For completing our purpose we have understanding of design and operation of an ALU as digital circuit, VHDL, Xilinx ISE for modeling of digital circuit and ISE for simulation of suitable circuit. In general computer architecture, the central processing unit of a computer is made of two main units, with several supporting systems; one of the two main units is called the ALU or arithmetic-logic unit. This structure takes inputs, performs various calculations operations on the inputs, and returns output. While the calculations can be as complex as desired, all ALUs work in this simple way. Other part is control part.In project we are implementing digital circuit on VHDL using Xilinx ISE IDE. This is only language and software based project. We are not going to implement this model on any programmable device such as FPGA and CPLD.